In the fabrication of integrated circuits, a number of well-established processes involve the application of ion beams to semiconductor wafers in vacuum. These processes include, for example, ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and is directed with varying degrees of acceleration toward a target wafer. Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded in the crystalline lattice of the semiconductor material to form a region of desired conductivity.
The target mounting site is a critical part of an ion implantation system. The target mounting site is required to firmly clamp a semiconductor wafer in a fixed position for ion implantation and, in most cases, to provide cooling of the wafer. In addition, means must be provided for exchanging wafers after completion of ion implantation. Cooling of wafers is particularly important in commercial semiconductor processing wherein a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput is to use a high current ion beam so that the implantation process is completed in a shorter time. However, large amounts of heat are likely to be generated by the high current ion beam. The heat can result in uncontrolled diffusion of impurities beyond prescribed limits in the wafer and in degradation of patterned photoresist layers. It is usually necessary to provide wafer cooling in order to limit the maximum wafer temperature to about 100.degree. C.
A number of techniques for clamping a semiconductor wafer at the target mounting site are known in the art. One known technique involves the use of electrostatic forces. A dielectric layer is positioned between a semiconductor wafer and a conductive support plate. A voltage is applied between the semiconductor wafer and the support plate, and the wafer is clamped against the dielectric layer by electrostatic forces. An electrostatic wafer clamp is disclosed by G. A. Wardly in "Electrostatic Wafer Chuck for Electron Beam Microfabrication", Rev. Sci. Instrum., Vol. 44, No. 10, Oct. 1972, pp. 1506-1509 and in U.S. Pat. No. 3,993,509 issued Nov. 23, 1976 to McGinty. Electrostatic wafer clamp arrangements which utilize a thermally-conductive material to remove heat from the wafer are disclosed in U.S. Pat. No. 4,502,094, issued Feb. 26, 1985 to Lewin et al., U.S. Pat. No. 4,665,463, issued May 12, 1987 to Ward et al., and U.S. Pat. No. 4,184,188, issued Jan. 15, 1980 to Briglia. The Briglia patent discloses a support plate having layers of thermally-conductive, electrically-insulative RTV silicone. Electrostatic wafer clamps are also disclosed in U.S. Pat. No. 4,480,284, issued Oct. 30, 1984 to Tojo et al., U.S. Pat. No. 4,554,611, issued Nov. 19, 1985 to Lewin, U.S. Pat. No. 4,724,510, issued Feb. 9, 1988 to Wicker et al. and U.S. Pat. No. 4,412,133, issued Oct. 25, 1983 to Eckes et al.
U.S. Pat. No. 4,520,421, issued May 28, 1985 to Sakitani et al., discloses a specimen supporting device including a pair of specimen attracting portions each having an electrode on the lower surface of an insulating member. When a voltage is applied between the pair of specimen attracting portions, the specimen is electrostatically attracted to the upper surface. The voltage can be AC or DC. An embodiment having eight arcuate specimen attracting portions with voltages of alternately opposite polarities is disclosed.
U.S. Pat. No. 5,103,367, issued Apr. 7, 1972 to Horowitz et al., discloses an electrostatic chuck for semiconductor wafers having at least three electrodes. Two of the electrodes embedded in a dielectric film are energized by an AC supply to provide sine wave fields of controlled amplitude and phase. The relative phases and amplitudes of the electrode voltages are adjusted to null the voltage induced on the surface of the wafer. In one embodiment, the substrate support surface comprises a thin ceramic layer such as sapphire (Al.sub.2 O.sub.3).
U.S. Pat. No. 5,166,856, issued Nov. 24, 1992 to Liporace et al., discloses an electrostatic chuck including a body of refractory metal sized to support a semiconductor wafer. A first layer of diamond coats the refractory metal body. A pair of generally planar electrodes is disposed on the first layer of diamond. A second layer of diamond conformally coats the electrodes. A DC voltage applied between the electrodes develops an electrostatic force to hold the wafer against the second diamond layer.
Problems associated with prior art electrostatic wafer clamping arrangements include inadequate clamping force, damage to devices on the wafer by charging currents, difficulty in making electrical contact to the semiconductor wafer, and wafer sticking to the platen after the clamping voltage has been removed. In addition, thermal transfer characteristics have usually been inadequate for high current ion implantation applications, since a significant portion of the platen surface area is devoted to making electrical contact with the semiconductor wafer. See, for example, the aforementioned U.S. Pat. No. 4,502,094.
An electrostatic wafer clamp that provides highly satisfactory performance is disclosed in U.S. Pat. No. 4,452,177, issued Sep. 19, 1995 to Frutiger. A six-phase electrostatic wafer clamp includes a platen having six symmetrically located electrodes. Voltages with six different phases are applied to the electrodes, with the voltages applied to electrodes on opposite sides of the platen being one-half cycle out of phase. The applied voltages are preferably bipolar square waves.
As semiconductor device geometries become progressively smaller and wafer sizes become progressively larger, the allowable particulate contamination specifications become more restrictive. The particulate performance of electrostatic wafer clamps is of particular concern because the wafers physically contact the surface of the wafer clamp and because the electrostatic forces which are employed to clamp wafers also attract particles. Accordingly, it is desirable to provide electrostatic wafer clamp configurations wherein particle generation and particulate contamination of wafers are extremely low.